The present invention relates to a semiconductor device wherein a semiconductor chip is electrically connected to a lower substrate and sealed, and a method for manufacturing the same.
In a conventional semiconductor device, a plurality of circuit wirings are provided in a wiring substrate or board used as a lower substrate formed of a glass epoxy resin containing glass fiber. A semiconductor chip is electrically connected to the circuit wirings and mounted thereto. The semiconductor chip mounted to the wiring board is sealed with a first encapsulating resin layer substantially equal to the wiring board in thermal expansion coefficient, followed by being heated, whereby it is temporarily cured. After the temporary curing of the first encapsulating resin layer, a second encapsulating resin layer formed of a high Tg resin matched with the wiring board in thermal expansion coefficient is applied so as to reach the thickness equivalent to the wiring board. The first and second encapsulating resin layers are thermoset and thereby manufactured. Excessive thermal expansion of the first encapsulating resin layer, which will exceed a glass transition temperature Tg upon heat treatment in a reflow process at the mounting of the semiconductor device to a mounting board or a printed circuit board, is suppressed by the second encapsulating resin layer not exceeding the glass transition temperature Tg to thereby prevent warpage of the semiconductor device.
There is also known a semiconductor device wherein after temporary curing of a first encapsulating resin layer, a high rigid member comprised of a metal or the like smaller than a range in which an encapsulating resin layer is applied, is disposed on the first encapsulating resin layer, followed by application of a second encapsulating resin layer, which in turn is thermoset to enhance the rigidity of the semiconductor device, thereby preventing warpage of the semiconductor device in a reflow process (refer to, for example, a patent document 1 (Japanese Unexamined Patent Publication No. Hei 10 (1998)-112515 (paragraph 0019 in page 4- paragraph 0031 in page 5 and paragraphs 0031-0033 in page 5, and FIGS. 1 and 3)).
However, a problem arises in that that when the technique of the patent document 1 referred to above is used for a lower substrate such as a silicon substrate whose thermal expansion coefficient is less than or equal to half the thermal expansion coefficient of the encapsulating resin layer, warpage caused by the difference between the thermal expansion coefficients of the silicon substrate and the encapsulating resin layer occurs in the semiconductor device when the silicon substrate equipped with the semiconductor chip is sealed with the encapsulating resin layer and cured by heating and cooled in its manufacturing process, i.e., the heat-cured encapsulating resin layer is more shrunk upon cooling to cause dish-shaped warpage in the semiconductor device.
Incidentally, the patent document 1 does not cause the above problem because the semiconductor chip mounted onto the wiring board formed of the glass epoxy resin is sealed with the first encapsulating resin layer approximately equal to the wiring board in thermal expansion coefficient.
Also the patent document 1 does not cause the above problem because since the high rigid member formed of the metal or the like (having a length of about half according to FIG. 3 in the patent document 1) smaller than the range in which the encapsulating resin layer is applied onto the first encapsulating resin layer, is disposed after the temporary curing of the first encapsulating resin layer, the amounts of shrinkage of the wiring board and the high rigid member reach the same degree because the length of the high rigid member less than or equal to half in thermal expansion coefficient is set to about half the length of the wiring board even though the second encapsulating resin layer is subsequently applied and thermoset.